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(R)
STLC3055
WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT
MONOCHIP SLIC OPTIMISED FOR WLL & ISDN-TA APPLICATIONS IMPLEMENT ALL KEY FEATURES OF THE BORSHT FUNCTION SINGLE SUPPLY (5.5 TO 15.8V) BUILT IN DC/DC CONVERTER CONTROLLER. SOFT BATTERY REVERSAL WITH PROGRAMMABLE TRANSITION TIME. ON-HOOK TRANSMISSION. PROGRAMMABLE OFF-HOOK DETECTOR THRESHOLD METERING PULSE GENERATION AND FILTER INTEGRATED RINGING INTEGRATED RING TRIP PARALLEL CONTROL INTERFACE (3.3V LOGIC LEVEL) PROGRAMMABLE CONSTANT CURRENT FEED SURFACE MOUNT PACKAGE INTEGRATED THERMAL PROTECTION -40 TO +85C OPERATING RANGE BLOCK DIAGRAM
D0 D1 D2
TQFP44 ORDERING NUMBERS: STLC3055Q STLC3055QTR
DESCRIPTION The STLC3055 is a SLIC device specifically designed for WLL (Wireless Local Loop) and ISDNTerminal Adaptors. One of the distinctive characteristic of this device is the ability to operate with a single supply voltage (from +5.5V to +15.8V) and self generate the negative battery by means of an on chip DC/DC converter controller that drives an external MOS switch. The battery level is properly adjusted depending on the operating mode. A useful characteristic for
DET
INPUT LOGICAND DECODER
OUTPUT LOGIC BGND
Status and functions
TIP TX RX ZAC1 ZAC RS ZB DC PROC
LINE OUTPUT
SUPERVISION AC PROC
DR IVER
STAGE
RING
CR EV
CSVR
CLK R SENSE GATE VF
DC/DC CKTTX CTTX1 CTTX2 FTTX CONV.
TTX PROC
REFERENCE
Vcc Vss
Agnd
CVCC VPOS
VOLT.
REG.
VBAT
Vbat
RTTX
CAC
ILTF RD IREF RLIM RTH
AGND
September 2000
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STLC3055
DESCRIPTION (continued) these applications is the integrated ringing generator. The control interface is a parallel type with open drain output and 3.3V logic levels. The metering pulses are generated on chip starting from two logic signals (0, 3.3V) one define the metering pulse frequency and the other the metering pulse duration. An on chip circuit then provides the proper shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed by external components. A dedicated cancellation circuit avoid posPIN CONNECTION
VBAT1
sible CODEC input saturation due to Metering pulse echo. Constant current feed can be set from 20mA to 40mA. Off-hook detection threshold is programmable from 5mA to 9mA. The device, developed in BCD100II technology (100V process), operates in the extended temperature range and integrates a thermal protection that sets the device in power down when Tj exceeds 140C.
44 D0 D1 D2 PD RES N.C. N.C. DET CKTTX CTTX1 CTTX2 1 2 3 4 5 6 7 8 9 10 11 12 RTTX
43
42
41
40
39
38
37
36
35
34 33 32 31 30 29 28 27 26 25 24 23 CSVR ILTF RD RTH IREF RLIM AGND CVCC VPOS RSENSE GATE
13 FTTX
14 RX
15 ZAC1
16 ZAC
17 RS
18 ZB
19 CAC
20 TX
21 VF
22 CLK
BGND
CREV
VBAT
RING
N.C.
N.C.
N.C.
N.C.
N.C.
TIP
D97TL279A
ABSOLUTE MAXIMUM RATINGS
Symbol Vpos A/BGND Vdig Tj Vbtot (1) Positive Supply Voltage AGND to BGND Pin D0, D1, D2, DET, CKTTX Max. junction Temperature Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device supply pins). Parameter Value -0.4 to +17 -1 to +1 -0.4 to 5.5 150 100 Unit V V V C V
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)
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STLC3055
OPERATING RANGE
Symbol Vpos A/BGND Vdig Top Vbat
(1)
Parameter Positive Supply Voltage AGND to BGND Pin D0, D1, D2, DET, CKTTX, PD Ambient Operating Temperature Range Self Generated Battery Voltage
Value 5.5 to +15.8 -100 to +100 -0.25 to 5.25 -40 to +85 -74 max.
Unit V V V C V
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)
THERMAL DATA
Symbol R th j-amb Parameter Thermal Resistance Junction to Ambient Typ. Value 60 Unit C/W
PIN DESCRIPTION
N. 25 34 27 16 15 17 18 20 14 19 32 41 37 28 30 29 43 Name VPOS BGND AGND ZAC ZAC1 RS ZB TX RX CAC ILTF TIP RING RLIM RTH IREF CREV Function Positive supply input ranging from 5.5V to 15.8V. Battery Ground, must be shorted with AGND. Analog Ground, must be shorted with BGND. AC impedance synthesis. RX buffer output, the AC impedance is connected from this node to ZAC. Protection resistors image (the image resistor is connected from this node to ZAC). Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this node to AGND. ZA impedance is connected from this node to ZAC1). 4 wire output port (TX output). The signal is referred to AGND. If connected to single supply CODEC input it must be DC decoupled with proper capacitor. 4 wire input port (RX input); 300K input impedance. This signal is referred to AGND. If connected to single supply CODEC output it must be DC decoupled with proper capacitor. AC feedback input, AC/DC split capacitor (CAC). Transversal line current image output. 2 wire port; TIP wire (Ia is the current sourced from this pin). 2 wire port; RING wire (Ib is the current sunk into this pin). Constant current feed programming pin (via RLIM). RLIM should be connected close to this pin and PCB layout should avoid noise injection on this pin. Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin and PCB layout should avoid noise injection on this pin. Internal bias current setting pin. RREF should be connected close to this pin and PCB layout should avoid noise injection on this pin. Reverse polarity transition time control. One proper capacitor connected between this pin and AGND is setting the reverse polarity transition time. This is the same transition time used to shape the "trapezoidal ringing" during ringing injection. DC feedback and ring trip input. RD should be connected close to this pin and PCB layout should avoid noise injection on this pin.
31
RD
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STLC3055
PIN DESCRIPTION (continued)
N. 4 26 35 23 21 22 Name PD CVCC VBAT GATE VF CLK Function Power Down input. Normally connected to CVCC (or to logic level high). Can be used to set TIP and Ring terminals in open circuit setting PD=0 and D0=D1=0. Internal positive voltage supply filter. Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted to VBAT1. Driver for external Power MOS transistor. Feedback input for DC/DC converter controller. Power Switch Controller Clock (typ. 125KHz). From version marked STLC3055 A5, this pin can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an internal auto-oscillation is internally generated and it is used instead of the external clock. When the CLK pin is connected to AGND, the GATE output is disabled. Voltage input for current sensing. RSENSE should be connected close to this pin and VPOS pin. The PCB layout should minimize the extra resistance introduced by the copper tracks. Control Interface: input bit 0. Control Interface: input bit 1. Control interface: input bit 2. Logic interface output of the supervision detector (active low). Battery supply filter capacitor. Metering pulse cancellation buffer output. TTX filter network should be connected to this point. If not used should be left open. Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering. Metering burst shaping external capacitor. Metering burst shaping external capacitor. Metering pulse clock input (12 KHz or 16KHz square wave). Frame connection. Must be shorted to VBAT. Reserved, must be connected to AGND. Not connected.
24 1 2 3 8 33 12 13 10 11 9 44 5 6, 7,36, 38,39, 40,42
RSENSE D0 D1 D2 DET CSVR RTTX FTTX CTTX1 CTTX2 CKTTX VBAT1 RES NC
FUNCTIONAL DESCRIPTION The STLC3055 is a device specifically developed for WLL and ISDN-TA applications. It is based on a SLIC core, on purpose optimised for these applications, with the addition of a DC/DC converter controller to fulfil the WLL and ISDN-TA design requirements. The SLIC performs the standard feeding, signalling and transmission functions. It can be set in three different operating modes via the D0, D1, D2 pins of the control logic interface (0 to 3.3V logic levels). The loop status is carried out on the DET pin (active low). The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels. The four possible SLIC's operating modes are: Power Down
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High Impedance Feeding (HI-Z) Active Ringing Table 1 shows how to set the different SLIC operating modes. Table 1. SLIC operating modes.
PD 0 1 1 1 1 1 1 D0 0 0 0 0 1 1 1 D1 0 0 1 1 1 1 0 D2 X X 0 1 0 1 0/1 Operating Mode Power Down H.I. Feeding (HI-Z) Active Normal Polarity Active Reverse Polarity Active TTX injection (N.P.) Active TTX injection (R.P.) Ring (D2 bit toggles @ fring)
STLC3055
The DC/DC converter controller is driving an external power MOS transistor (P-Channel) in order to generate the negative battery voltage needed for device operation. The DC/DC converter controller is synchronised with an external CLK (125KHZ typ.). From version marked STLC3055 A5, it can be synchronised to an internal clock generated when the pin CLK is connected to CVCC. One sensing resistor in series to Vpos supply allows to fix the maximum allowed input peak current. This feature is implemented in order to avoid overload on Vpos supply in case of line transient (ex. ring trip detection). The typical value is obtained for a sensing resistor equal to 110m that will guarantee an average current consumption from Vpos < 700mA. When in on-hook the self generated battery voltage is set to a predefined value. This value can be adjusted via one external resistor (RF1) and it is typical -50V. When RING mode is selected this value is increased to -70V typ. Once the line goes in off-hook condition, the DC/DC converter automatically adjust the generated battery voltage in order to feed the line with a fixed DC current (programmable via RLIM) optimising in this way the power dissipation. This operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum. The output voltage in on-hook condition is equal to the self generated battery voltage (-50V typ). When off-hook occurs the DET becomes active (low logic level). The off-hook threshold in HI-Z mode is the same value as programmed in ACTIVE mode. The DC characteristic in HI-Z mode is just equal to the self generated battery with 2x(1500W+Rp) in series (see fig.1), where Rp is the external protection resistance. Figure 1. DC Characteristic in HI-Z Mode.
IL Vbat 2x(R1+Rp) Slope: 2x(R1+Rp) (R1=1500ohm)
VL
OPERATING MODES Power Down DC CHARACTERISTIC & SUPERVISION When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance. Also the line detectors are disabled therefore the off-hook condition cannot be detected. This mode can be selected in emergency condition when it is necessary to cut any current delivered to the line. This mode is also forced by STLC3055 in case of thermal overload (Tj > 140C). In this case the device goes back to the previous status as soon as the junction temperature decrease under the hysteresis threshold. AC CHARACTERISTICS The 2W port is set in high impedance, the TX output buffer is a low impedance output, no AC transmission is possible.
Vbat (-50V)
AC CHARACTERISTICS The AC impedance shown at the 2W port (TIP/RING) is the same as the DC one. The TIP/RING AC impedance will be 2x(1500 + Rp) or high impedance.
High Impedance Feeding (HI-Z) DC CHARACTERISTIC & SUPERVISION
Active DC CHARACTERISTICS & SUPERVISION When this mode is selected the STLC3055 provides both DC feeding and AC transmission. The STLC3055 feeds the line with a constant current fixed by RLIM (20mA to 40mA range). The on-hook voltage is typically 40V allowing on-hook transmission; the self generated Vbat is -50V typ. If the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the STLC3055 behaves like a 40V voltage source with a series impedance equal to the protection resistors 2xRp (typ. 2x41) plus the internal resistance. Fig. 2 shows the typical DC characteristic in ACTIVE mode.
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STLC3055
Figure 2. DC characteristic in ACTIVE mode IL Ilim (20 to 40mA)
2Rp
POLARITY REVERSAL The D2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way. This means that the TIP and RING wire exchange their polarities following a ramp transition (see fig.3). The transition time is controlled by an external capacitor CREV. This capacitor is also setting the shape of the ringing trapezoidal waveform. When the control pins set battery reversal the line polarity is reversed with a proper transition time set via an external capacitor (CREV). Figure 3. TIP/RING typical transition from Direct to Reverse Polarity
10V
VL
Vbat (-50V)
The line status (on/off hook) is monitored by the SLIC's supervision circuit. The off-hook threshold can be programmed via the external resistor RTH in the range from 5mA to 9mA. Independently on the programmed constant current value, the TIP and RING buffers have a current source capability limited to 70mA typ. Moreover the power available at Vbat is controlled by the DC/DC converter that limits the peak current drawn from the Vpos supply. The maximum allowed current peak is set by the RSENSE resistor and it is typically 900mApk. AC CHARACTERISTICS The SLIC provides the standard SLIC transmission functions: Input impedance synthesis: can be real or complex and is set by a scaled (x50) external ZAC impedance. Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the TX output with a -6dB gain and from the RX input to the 2W port with a 0dB gain. 2 to 4 wire conversion: The balance impedance can be real or complex, the proper cancellation is obtained by means of two external impedance ZA and ZB. Once in Active mode (D1=1) the SLIC can operate in different states setting properly D0 and D2 control bits (see also Table 2). Table 2. SLIC states in ACTIVE mode
D0 0 0 1 1 6/22 D1 1 1 1 1 D2 0 1 0 1 Operating Mode Active Normal Polarity Active Reverse Polarity Active TTX injection (N.P.) Active TTX injection (R.P.)
GND TIP
4V typ.
40V typ ON-HOOK
dV/dT set by CREV RING
METERING PULSE INJECTION (TTX) The metering pulses circuit consist of a burst shaping generator that gives a square wave shaped and a low pass filter to reduce the harmonic distortion of the output signal. The metering pulse is obtained starting from two logic signals: CKTTX: is a square wave at the TTX frequency (12 or 16KHz) and should be permanently applied to the CKTTX pin or at least for all the duration of the TTX pulse (including rising and decay phases). D0: enable the TTX generation circuit and define the TTX pulse duration. This two signals are then processed by a dedicated circuitry integrated on chip that generate the metering pulse as an amplitude modulated shaped squarewave (SQTTX) (see fig.4). Both the amplitude and the envelope of the squarewave (SQTTX) can be programmed by means of external components. In particular the amplitude is set by the two resistors RLV and the
STLC3055
Figure 4. Metering pulse generation circuit. Low Pass Filter
CTTX1
C1
RLV BURST
SHAPING GENERATOR
CS
SQTTX
R1 CFL
R2 FTTX OP1
+
RTTX
C2 Sinusoidal wave pulse metering
RLV
CTTX2 D0 CKTTX
Required external components vs. filter order.
Order CFL 1 2 3 X X
R1
C!
R2
C2
THD 13%
X X
X X
X X
X X
6% 3%
Square wave pulse metering
shaping by the capacitor CS. The waveform so generated is then filtered and injected on the line. The low pass filter can be obtained using the integrated buffer OP1 connected between pin FTTX (OP1 non inverting input) and RTTX (OP1 output) (see fig.4) and implementing a "Sallen and Key" configuration. Depending on the external components count it is possible to build an optimised application depending on the distortion level required. In particular harmonic distortion levels equal to 13%, 6% and 3% can be obtained respectively with first, second and third order filters (see fig.4). The circuit showed in the "Application diagram" is related to the simple first order filter. Once the shaped and filtered signal is obtained at RTTX buffer output it is injected on the TIP/RING pins with a +6dB gain. It should be noted that this is the nominal condition obtained in presence of ideal TTX echo cancellation (obtained via proper setting of RTTX and CTTX). In addition the effective level obtained on the line will depend on the line impedance, the protection resistor value and the series switch (SW1 or SW2) on resistance. In the typical application (TTX line impedance =200 , RP = 41, SW1,2 on resistance = 9 and ideal TTX echo cancellation) the metering pulse level on the line will be 1.33 times the level applied to the RTTX pin.
As already mentioned the metering pulse echo cancellation is obtained by means of two external components (RTTX and CTTX) that should match the line impedance at the TTX frequency. This simple network has a double effect: Synthesise a low output impedance at the TIP/RING pins at the TTX frequency. Cut the eventual TTX echo that will be transferred from the line to the TX output. Ringing When this mode is selected STLC3055 self generate an higher negative battery (-70V typ.) in order to allow a balanced ringing signal of typically 65Vpeak. In this condition both the DC and AC feedback loop are disabled and the SLIC line drivers operate as voltage buffers. The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in fact controls the line polarity (0=direct; 1=reverse). As in the ACTIVE mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see fig.5). The shaping is defined by the CREV external capacitor. Selecting the proper capacitor value it is possible to get different crest factor values. The following table shows the crest factor values
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STLC3055
Figure 5. TIP/RING typical ringing waveform If for any reason the ringer load will be too high the self generated battery will drop in order to keep the power consumption to the fixed limit and therefore also the ring voltage level will be reduced. In the typical application with RSENSE = 110m the peak current from Vpos is limited to about 900mA, which correspond to an average current of 700mA max. In this condition the STLC3055 can drive up to 3REN with a ring frequency fr=25Hz (1REN = 1800 + 1.0F, European standard). In order to drive up to 5REN (1REN= 6930 + 8F, US standard) it is necessary to modify the external components as follows: CREV = 15nF RD = 2.2K
GND TIP
2.5V typ.
65V typ.
dV/dT set by CREV RING VBAT
2.5V typ.
obtained with a 20Hz and 25Hz ring frequency and with 1REN. This value are valid either with European or USA specification:
CREV 22nF 27nF 33nF CREST FACTOR @20Hz 1.2 1.25 1.33 CREST FACTOR @25Hz 1.26 1.32 Not significant (*)
(*) Distorsion already less than 10%.
Power On Requirements In order to avoid damage to the device when Vpos is first applied it is recommended to keep all the logic inputs to a low logic level (0V) until Vpos is >5.5V. In case this power up sequence cannot be guaranteed it's recommended to connect a shottky diode (BAT46 or equivalent) between VBAT and BGND see figure below. Figure 6. Shottky diode connection
The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. It should be noted that such a method is optimised for operation on short loop applications and may not operate properly in presence of long loop applications (> 500 ). Once ring trip is detected, the DET output is activated (logic level low), at this point the card controller or a simple logic circuit should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3055 in the proper operating mode (normally ACTIVE). RING LEVEL IN PRESENCE OF MORE TELEPHONE IN PARALLEL As already mentioned above the maximum current that can be drawn from the Vpos supply is controlled and limited via the external RSENSE. This will limit also the power available at the self generated negative battery.
BGND
STLC3055
VBAT
BAT46
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STLC3055
Layout Recommendation A properly designed PCB layout is a basic issue to guarantee a correct behaviour and good noise performances. Particular care must be taken on the ground connection and in this case the star configuration allows surely to avoid possible problems (see Application Diagram Fig. 7). The ground of the power supply (VPOS) has to be connected to the center of the star, let's call this point PGND. This point should show a resistance as low as possible, that means it should be a ground plane. Noise sources can be identified in not enough good grounds, not enough low impedance supplies and parasitic coupling between PCB tracks and high impedance pins of the device. In particular to avoid noise problems the layout should prevent any coupling between the DC/DC converter components and analog pins that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). As a first reccomendation the components CV, L, D1, CVPOS, RSENSE should be kept as close as possible to each other and isolated from the other components. Additional improvements can be obtained: decoupling the center of the star from the analog ground of STLC3055 using small chokes. adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch frequency on VPOS. External Components List In order to properly define the external components value the following system parameters have to be defined:
The AC input impedance shown by the SLIC at the line terminals "Zs" to which the return loss measurement is referred. It can be real (typ. 600) or complex. The AC balance impedance, it is the equivalent impedance of the line "Zl" used for evaluation of the trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance. The value of the two protection resistors Rp in series with the line termination. The line impedance at the TTX frequency "Zlttx". The metering pulse level amplitude measured at line termination "V LOTTX". In case of low order filtering, VLOTTX represents the amplitude (Vrms) of the fundamental frequency component. (typ 12 or 16KHz). Pulse metering envelope rise and decay time constant "". The slope of the ringing waveform "VTR/T ". The value of the constant current limit current "Ilim". The value of the off-hook current threshold "ITH". The value of the ring trip rectified average threshold current "I RTH". The value of the required self generated negative battery "V BATR" in ring mode (max value is 70V). This value can be obtained from the desired ring peak level + 5V. The value of the maximum current peak sunk from Vpos "IPK".
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STLC3055
EXTERNAL COMPONENTS
Name RREF CSVR RD CAC RP RS ZAC ZA (1) ZB (1) CCOMP CH RLIM RTH CREV RTTX (3) CTTX (3) RLV CS CFL Function Bias setting current Negative Battery Filter Ring Trip threshold setting resistor AC/DC split capacitance Line protection resistor Protection and series switches resistance image Two wire AC impedance SLIC impedance balancing network Line impedance balancing network AC feedback loop compensation Trans-Hybrid Loss frequency compensation Current limiting programming Off-hook threshold programming (ACTIVE mode) Reverse polarity transition time programming Pulse metering cancellation resistor Pulse metering cancellation capacitor Pulse metering level resistor Pulse metering shaping capacitor Pulse metering filter capacitor Rp > 30 RS = 100 (Rp + 9) ZAC = 50 (Zs - 2Rp - 18) ZA = 50 Zs ZB = 50 Zl CCOMP = 1/(2fo100(RP+9)) fo = 250kHz CH = CCOMP RLIM = 1300/Ilim 32.5k < RLIM < 65k RTH = 260/ITH 27k < RTH < 52k CREV = (1/3750) T/VTR) RTTX = 50Re[(Zlttx+2Rp+18)] CTTX = 1/{502fttx[-lm(Zlttx)]} RLV = 63.310 VLOTTX = (|Zlttx + 2Rp + 18|/|Zlttx|) CS = /(2RLV) CFL = 2/(2fttxRLV)
3
Formula RREF = 1.3/Ibias Ibias = 50A CSVR = 1/(2 fp 1.8M) fp = 50Hz RD = 100/IRTH 2K < RD < 5K
Typ. Value 26k 1% 1.5nF 10% 100VL 4.12k 1% @ IRTH = 24mA 22F 20% 15VL @ RD = 4.12k 41 1% 5k @ Rp = 41 25k 1% @ Zs = 600 30k 1% @ Zs = 600 30k 1% @ Zl = 600 120pF 10% 10VL @ Rp = 41 120pF 10% 10VL 52.3k 1% @ Ilim = 25mA 28.7k 1% @ITH = 9mA 22nF 10% 10V @ 12V/ms 15k @Zlttx = 200 real 100nF 10% 10V (2) @ Zlttx = 200 real 27k 1% @ VLOTTX = 275mVrms 100nF 10% 10V @ = 6ms, RLV = 27.1k 1nF 10% 10V @fttx = 12kHz RLV = 27k 100k 100nF 20% 10V 100F(4)
RDD CVCC CVpos
Pull up resistors Internally supply filter capacitor Positive supply filter capacitor with low impedance for switch mode power supply Battery supply filter capacitor with low impedance for switch mode power supply High frequency noise filter
CV
100F 20% 100V (5)
CVB
470nF 20% 100VL
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STLC3055
EXTERNAL COMPONENTS (continued)
Name CRD (6) Q1 Function High frequency noise filter DC/DC converter switch P ch. MOS transistor RDS(ON)1.2,VDS = -100V Total gate charge=20nC max. with VGS=4.5V and VDS=1V ID>500mA Vr > 100V, tRR 50ns RSENSE = 100mV/IPK DC Resistance 0.1 (9) Formula Typ. Value 100nF 10% 15VL Possible choiches: IRF9510 or IRF9520 or IRF9120 or equivalent SMBYW01-200 or equivalent 110m @IPK = 900mA L=125H RFP1304PV (Manuf.: All Inductive) or SUMIDA CDRH125 or equivalent 220pF to 470pF (10) 250KD1 RSENSE L (8)
DC/DC converter series diode DC/DC converter peak current limiting DC/DC converter inductor
CF1 RF1 RF2
DC/DC converter feedback loop stability Negative battery programming level Negative battery programming level
(1) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|. (2) In this case CTTX is just operating as a DC decoupling capacitor (fp=100Hz). (3) Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula: ZTTX=50*(Zlttx+2Rp+18). (4) CVpos should be defined depending on the power supply current capability and maximum allowable ripple. (5) For low ripple application use 2x47F in parallel. (6) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input). (7) RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as follows:
267k VBAT(ACTIVE) VBATR(RING) -46V -62V
280k -48V -65V
294kW -49V -68V
300k -50V -70V
VBATR should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.). The above relation is valid provided that the Vpos power supply current capability and the RSENSE programming allow to source all the current requested by the particular ringer load configuration. (8) Core: MICROMETALS T50-26C IRON POWDER, AL-VALUE 61nH/N2 Current rating: 2A (50/60Hz) Operating Temperature -25 to +60 Centigrades Inductance: 14H +/-15% at 1KHz, 1mA DC resistance of winding: MAX.100 mOhm Code: RFY1303 Wire: UEW2, 0,60 mm Turns: 50 Inductance (f=1KHz): >125H (9) For high efficiency in HI-Z mode coil resistance @125kHz must be <3ohm (10) Function of this capacitor is to introduce a zero at the resonance frequency for loop stability. In case some parasitic resistance are already present in the loop (Coil, CVBAT, PCB layout), the presence of this capacitor can degrade the device noise performances; in this case CF1 should be removed being the loop stability already guaranteed by the parasitic resistance.
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STLC3055
Figure 6. Application Diagram.
CVCC RX TX VPOS CVPOS RSENSE
RS
RX RS ZAC
TX
AGND BGND
CVCC
VPOS RSENSE GATE D1 VBAT CVB CF1 RF1 CV RF2 L Q1
CCOMP ZAC ZA
ZAC1
ZB CH VDD RDD ZB
VF
CLK TIP
CLK RP TIP RP RING
CONTROL INTERFACE
DET D0 D1 D2
DET D0 D1 D2
STLC3055
RING
CSVR CREV CREV RTH RLIM IREF RREF RTTX CAC ILTF RD RLIM RTH CSVR
TTX CLOCK RLV
CKTTX CTTX1 RLV CS CTTX2 FTTX CFL
RTTX AGND BGND SUPPLY GND SUGGESTED GROUND LAY-OUT CTTX CAC
RD
CRD
D96TL275D
PGND
Figure 7. Application Diagram without Metering Pulse Generation.
CVCC RX TX VPOS CVPOS RSENSE
RS
RX RS ZAC
TX
AGND BGND
CVCC
VPOS RSENSE GATE D1 VBAT CVB CF1 RF1 CV RF2 L Q1
CCOMP ZAC ZA
ZAC1
ZB CH VDD RDD ZB
VF
CLK
CLK RP TIP RP RING
STLC3055
CONTROL INTERFACE DET D0 D1 D2 DET D0 D1 D2
TIP RING
CSVR CREV CREV RTH RLIM IREF RREF RTTX CAC ILTF RD RLIM RTH CSVR
CKTTX CTTX1 CTTX2 FTTX
RD AGND BGND SUPPLY GND SUGGESTED GROUND LAY-OUT CAC
CRD
D98TL380B
PGND
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STLC3055
ELECTRICAL CHARACTERISTICS Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85C.
DC CHARACTERISTICS Symbol Vlohi Parameter Line voltage Test Condition Il = 0, HI-Z (High impedance feeding) T amb = 0 to 85C Il = 0, HI-Z (High impedance feeding) T amb = -40 to 85C Il = 0, ACTIVE T amb = 0 to 85C Il = 0, ACTIVE T amb = -40 to 85C Min. 44 Typ. 50 Max. Unit V
Vlohi
Line voltage
42
48
V
Vloa Vloa Ilim Ilima
Line voltage Line voltage
33 31 20 -10
40 37 40 10
V V mA mA
Lim. current programming range ACTIVE mode Lim. current accuracy ACTIVE mode. Rel. to programmed value 20mA to 40mA HI-Z (High Impedance feeding)
Rfeed HI Zrx
Feeding resistance RX port input impedance
2.4 280
3.6
k k
AC CHARACTERISTICS L/T Long. to transv. (see Appendix for test circuit) Transv. to long. (see Appendix for test circuit) Transv. to long. (see Appendix for test circuit) 2W return loss Trans-hybrid loss Rp = 41, 1% tol., ACTIVE N. P., R L = 600 (*) f = 300 to 3400Hz Rp = 41, 1% tol., ACTIVE N. P., R L = 600 (*) f = 300 to 3400Hz Rp = 41, 1% tol., ACTIVE N. P., R L = 600 (*) f = 1kHz 300 to 3400Hz, ACTIVE N. P., R L = 600 (*) 300 to 3400Hz, 20Log|VRX/VTX|, ACTIVE N. P., R L = 600 (*) at line terminals on ref. imped. ACTIVE N. P., R L = 600 (*) ACTIVE N. P., R L = 600 (*) 0dBm @ 1020Hz, ACTIVE N. P., R L = 600 (*) 0dBm @ 1020Hz, ACTIVE N. P., R L = 600 (*) rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., R L = 600 (*) 48 50 dB
T/L
40
45
dB
T/L
48
53
dB
2WRL THL
22 30
26
dB dB
Ovl TXoff G24 G42 G24f
2W overload level TX output offset Transmit gain abs. Receive gain abs. TX gain variation vs. freq.
10 -150 -6.4 -0.4 -0.12 150 -5.6 0.4 0.12
dBm mV dB dB dB
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STLC3055
ELECTRICAL CHARACTERISTICS (continued)
Symbol G42f Parameter RX gain variation vs. freq. Test Condition rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., R L = 600 (*) psophometric filtered ACTIVE N. P., R L = 600 (*) T amb = 0 to +85C psophometric filtered ACTIVE N. P., R L = 600 (*) T amb = -40 to +85C psophometric filtered ACTIVE N. P., R L = 600 (*) T amb = 0 to +85C psophometric filtered ACTIVE N. P., R L = 600 (*) T amb = -40 to +85C ACTIVE N. P., R L = 600 (*) ACTIVE - TTX Zl = 200 fttx = 12kHz 200 -10% 250 125 10% Min. -0.12 Typ. Max. 0.12 Unit dB
V2Wp
Idle channel noise at line
-73
-68
dBmp
V2Wp
Idle channel noise at line
-68
dBmp
V4Wp
Idle channel noise at line
-75
-70
dBmp
V4Wp
Idle channel noise at line
-75
dBmp
Thd VTTX CLKfreq
Total Harmonic Distortion Metering pulse level on line CLK operating range
-46
dB mVrms kHz
(*) RL: Line Resistance
RING Vring Line voltage RING D2 toggling @ fr = 25Hz Load = 3REN; Crest Factor = 1.25 1REN = 1800 + 1.0F T amb = 0 to +85C RING D2 toggling @ fr = 25Hz Load = 3REN; Crest Factor = 1.25 1REN = 1800 + 1.0F T amb = -40 to +85C 45 49 Vrms
Vring
Line voltage
44
48
Vrms
DETECTORS IOFFTHA ROFTHA IONTHA RONTHA IOFFTH I ROFFTHI IONTHI RONTHI Off/hook current threshold Off/hook loop resistance threshold On/hook current threshold On/hook loop resistance threshold Off/hook current threshold Off/hook loop resistance threshold On/hook current threshold On/hook loop resistance threshold ACT. mode, RTH = 28.7k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 28.7k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 28.7k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 28.7k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 28.7k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 28.7k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 28.7k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 28.7k 1% (Prog. ITH = 9mA) 8 8 10.5 800 6 10.5 3.4 6 mA k mA k mA mA k
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STLC3055
ELECTRICAL CHARACTERISTICS (continued)
Symbol Irt Irta Trtd Td Rlrt (1) ThAl Parameter Ring Trip detector threshold range Ring Trip detector threshold accuracy Ring trip detection time Dialling distortion Loop resistance Tj for th. alarm activation 160 RING RING RING ACTIVE -1 Test Condition Min. 20 -15 TBD 1 500 Typ. Max. 50 15 Unit mA % ms ms C
(1) Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection.
DIGITAL INTERFACE INPUTS: D0, D1, D2, PD, CLK OUTPUTS: DET Vih Vil Iih Iil Vol In put high voltage Input low voltage Input high current Input low current Output low voltage Iol = 1mA -10 -10 2 0.8 10 10 0.45 V V A A V
PSRR AND POWER CONSUMPTION PSERRC Ivpos Power supply rejection Vpos to 2W port Vpos supply current @ ii = 0 Vripple = 100mVrms 50 to 4000Hz HI-Z On-Hook ACTIVE On-Hook, RING (line open) RING Off-Hook RSENSE = 110m -20% 26 36 52 93 120 950 60 115 140 +20% dB mA mA mA mApk
Ipk
Peak current limiting accuracy
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STLC3055
APPENDIX A
STLC3055 Test Circuits Referring to the application diagram shown in fig. 7 of the STLC3055 datasheet and using as external components the Typ. Values specified in the "External Components" Table (page 13) find below the proper configuration for each measurement. All measurements requiring DC current termination should be performed using "Wandel & Goltermann DC Loop Holding Circuit GH-1" or equivalent. Figure A1. 2W Return Loss 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs)
W&G GH1 Zref TIP 600ohm 100F Vs 1Kohm E
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3055 application circuit
1Kohm
100F RING RX
Figure A2. THL Trans Hybrid Loss THL = 20Log|Vrx/Vtx|
W&G GH1 TIP 100F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx
600ohm
STLC3055 application circuit
100F RING RX Vrx
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STLC3055
Figure A3. G24 Transmit Gain G24 = 20Log|2Vtx/E|
W&G GH1 TIP 100F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx
600ohm
STLC3055 application circuit
E 100F RING RX
Figure A4. G42 Receive Gain G42 = 20Log|VI/Vrx|
W&G GH1 TIP 10 0F Vl 600ohm
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3055 application circuit
10 0F RING RX Vrx
Figure A5. PSRRC Power supply rejection Vpos to 2W port PSSRC = 20Log|Vn/Vl|
W&G GH1 TIP 100F Vl 600ohm
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3055 application circuit
100F RING VPOS RX
~
Vn
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STLC3055
Figure A6. L/T Longitudinal to Transversal Conversion L/T = 20Log|Vcm/Vl|
W&G GH1 300ohm 100F TIP 100F
100mA DC max
TX
Impedance matching better than 0.1%
Vcm
Vl
Zin = 100K 200 to 6kHz
STLC3055 application circuit
100F RING RX
300ohm
100F
Figure A7. T/L Transversal to Longitudinal Conversion T/L = 20Log|Vrx/Vcm|
300ohm
100F
W&G GH1 TIP 100F
100mA DC max
TX
Impedancematching better than 0.1%
Zin = 100K 200 to 6kHz
STLC3055 application circuit
600ohm
Vcm
100F RING RX Vrx
300ohm
100F
Figure A8. VTTX Metering Pulse level on line
TIP
TX
Vlttx 200ohm
STLC3055 application circuit
RING CKTTX
RX
fttx (12 or 16kHz)
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STLC3055
Figure A9. V2Wp and W4Wp: Idle channel psophometric noise at line and TX. V2Wp = 20Log|Vl/0.774l|;V4Wp = 20Log|Vtx/0.774l|
W&G GH1 TIP 100F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx psophometric filtered
600ohm Vl psophometric filtered
STLC3055 application circuit
100F RING RX
APPENDIX B
STLC3055 Overvoltage Protection Figure B1. Simplified configuration for indoor overvoltage protection
BGND
STLC3055
2x SM4T39RX TIP RING RP1 RP1 RP2 RP2 TIP RING
VBA T
RP2: Fuse or PTC
Figure B2. Standard overvoltage protection configuration for K20 compliance
BGND
STLC3055
2x SM4T39RX TIP RP1 LCP1511 RING RP1 RP2 RING RP2 TIP
VBAT
RP2: Fuse or PTC
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STLC3055
APPENDIX C TYPICAL STATE DIAGRAM FOR STLC3055 OPERATION Figure C1.
Tj>Tth PD=0, D0=D1=0
Normally used for On Hook Transmission Active On Hook Ring Pause D0=0, D1=1, D2=0
Power Down
Ring Burst
Ring Burst D0=1, D1=0, D2=0/1 Ringing
PD=1, D0=D1=0 On Hook Detection for T>Tref HI-Z Feeding Active Off Hook Off Hook Detection D0=0, D1=1, D2=0 Ring Trip Detection
On Hook Condition
Off Hook Detection
Note: all state transitions are under the microprocessor control.
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STLC3055
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STLC3055
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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